	// verilator_coverage annotation
	module reg_ex_mem(
 020001	    input  wire clk,
%000001	    input  wire rst,
 000629	    input  wire[31:0] ex_regs_data2,
 000639	    input  wire[31:0] ex_alu_o,
 000083	    input  wire[4:0]  ex_rd,
 000013	    input  wire       ex_mem_read,
 000013	    input  wire       ex_mem2reg,
%000002	    input  wire       ex_mem_write,
 000024	    input  wire       ex_regs_write,
 000041	    input  wire[2:0]  ex_func3_code, 
	
	    //forwarding
 000096	    input wire[4:0]   ex_rs2,
 000097	    output reg[4:0]   me_rs2,
	
 000631	    output reg[31:0]  me_regs_data2,
 000658	    output reg[31:0]  me_alu_o,
 000083	    output reg[4:0]   me_rd,
 000012	    output reg        me_mem_read,
 000013	    output reg        me_mem2reg,
%000003	    output reg        me_mem_write,
 000023	    output reg        me_regs_write,
 000040	    output reg[2:0]   me_func3_code,
	
%000002	    input wire ex_m_write,
%000002	    output reg me_m_write,
 000038	    input wire [1:0] ex_m_w_index,
 000038	    output reg [1:0] me_m_w_index,
 000291	    input wire [31:0] ex_m_data,
 000288	    output reg [31:0] me_m_data,
 026368	    input wire [6:0] ex_inst_opcode,
 026361	    output reg [6:0] me_inst_opcode,
%000282	    input wire[31:0] matrix_mopa_o[3:0],
%000422	    output reg [31:0] me_matrix_mopa_o[3:0],
%000002	    input wire ex_matrix_mopa_en,
%000003	    output reg me_matrix_mopa_en
	);
	
	always @(posedge clk) begin
 000100	    if (!rst)begin
	        me_regs_data2  <= 0;         
	        me_alu_o       <= 0;     
	        me_rd          <= 0; 
	        me_mem_read    <= 0;     
	        me_mem2reg     <= 0;     
	        me_mem_write   <= 0;         
	        me_regs_write  <= 0;  
	        me_rs2         <= 0;   
	        me_func3_code  <= 0;    
	        me_m_write     <= 0;
	        me_m_w_index     <= 0;
	        me_m_data      <= 0;
	        me_inst_opcode  <= 0;
	        me_matrix_mopa_o[0] <= 0;
	        me_matrix_mopa_o[1] <= 0;
	        me_matrix_mopa_o[2] <= 0;
	        me_matrix_mopa_o[3] <= 0;
	        me_matrix_mopa_en <= 0;
	    end 
 009900	    else begin  
	        me_regs_data2  <= ex_regs_data2;         
	        me_alu_o       <= ex_alu_o;     
	        me_rd          <= ex_rd; 
	        me_mem_read    <= ex_mem_read;     
	        me_mem2reg     <= ex_mem2reg;     
	        me_mem_write   <= ex_mem_write;         
	        me_regs_write  <= ex_regs_write;
	        me_rs2         <= ex_rs2;    
	        me_func3_code  <= ex_func3_code; 
	        me_m_write     <= ex_m_write;
	        me_m_w_index     <= ex_m_w_index;
	        me_m_data      <= ex_m_data;
	        me_inst_opcode <= ex_inst_opcode;
	        me_matrix_mopa_o[0] <= matrix_mopa_o[0];
	        me_matrix_mopa_o[1] <= matrix_mopa_o[1];
	        me_matrix_mopa_o[2] <= matrix_mopa_o[2];
	        me_matrix_mopa_o[3] <= matrix_mopa_o[3];
	        me_matrix_mopa_en <= ex_matrix_mopa_en;
	    end
	
	    $display("me_alu_o: %h",me_alu_o);
	
	end
	
	endmodule
	
